I. Field of the Invention
This invention relates to data processing systems and specifically to multiple computers that communicate with one another via information buses.
II. Description of the Prior Art
Most existing computers in their different forms are sequential Von Neumann machines that perform only one step at a time. This leads to excessive delays in multi-user systems. Since the 1940s emphasis has been placed on increasing computer speeds with faster and denser circuit components. There are many computer experts and researchers trying to redesign the basics of computer structure to overcome heretofore sequential processing limitations. Conventional stored program computers are generally composed in three main parts - a Central Processing Unit (CPU), Common Memory and an Input/Output section. When such conventional computers were first introduced they could only run one program at a time. A Central Processing Unit (CPU) when operating in sequential fashion will execute only one instruction at a time. However, with the advent of semiconductors and later intergrated circuitry, CPUs have become fast enough to efficiently enable time sharing in their execution of instructions. This has lead to the development of multi-tasking operating systems allowing several programs to run in a time shared mode within one computer. Further development of these operating systems progressed from time-sharing memory to simulating large main memories by swapping data with rotating storage components and, thereby, providing a virtual memory operating system.
This has not been accomplished without its problems and that the added burden of simulation accomplished with such operating systems takes its toll in available memory and computing power. Inherently, as operating systems increase in capability, the host computer using such an operating system decreases in capability, a result certainly not desired. For this reason and many others there has been a continuing need for increasing more powerful and faster Central Processing Units. There are, however, practical factors of space, time and technology limiting the execution speed that a single CPU can attain.
In an approach to resolve some of these problems, CPUs have attained increased performance and speed not only as a result of advances in integrated circuit technology but also by adding processors together. In such a CPU with many processors, each processor accomplishes certain tasks but retains appearance of a single CPU architecture with greatly increased performance. Another approach providing more power of speed is the attachment of Auxiliary Processing Units to a Central Processor. This offers additional freedom of implementation and may allow processes to execute concurrently (at the same instant in time). Most attached processing systems, however, tie input/output and scheduling functions directly to the main CPU disallowing direct programmability of the attached processors.
In such a system the CPUs communicate via an Information Bus which is several signal lines connected in parallel to the CPUs. The Information Bus must include a signal protocol which defines what the different signals mean and the timing of the signals. Such an Information Bus is the VME Bus including the VME protocol definition. This Information Bus has been established as a standard and interfacing to the VME Bus has been made easier through products such as the XVME-080 Intelligent Prototyping Module by XYCOM that provides a means to interface a CPU to the VME Bus.
However, the VME Bus does include certain disadvantages. One disadvantage is the difficulty of passing a large amount of information traffic between a multiple of CPUs in a short time frame. While typing multiple VME buses together may seem to solve this difficulty, a contention problem results when a first CPU on a first VME Bus attempts to access a second CPU on a second VME Bus at the time the second CPU is attempting to access the first CPU. The present invention removes this difficulty while providing for high speed information transfer between several CPUs in a short time frame.
It is an object of the present invention to provide an arrangement that facilitates communication between a multiple of computer units.
It is also an object of the present invention to provide an arrangement that includes scalable units permitting system configurations of varying size and capabilities and further permitting ease of system reconfiguration by providing plugably connectable units such as computer cards, memory cards, and other cards that may be connected to or removed from an information transfer bus arrangement that provides fast and efficient communications between the connected units.
It is a further object of the invention to provide a monitor arrangement permitting a system unit to individually or collectively monitor and control the operation of the system.